C H A P T E R 5 - Hardware and Functional Description

C H A P T E R 5

Hardware and Functional Description

This chapter contains the following sections:

Section 5.1, Summarized Physical Description

Section 5.2, Detailed Description

Section 5.3, CPU and Main Memory Subsystems

Section 5.4, Bus Subsystems

Section 5.5, System Input/Output

Section 5.6, System Management Controller

Section 5.7, Resets

Section 5.8, Power Subsystem

Section 5.9, CompactPCI Interface

Section 5.10, Interrupts

Section 5.11, Chip-Select PLD Registers

Section 5.12, SMC PLD Registers

5.1 Summarized Physical Description

The Netra CP2160 board is a 6U-sized CompactPCI circuit card with CompactPCI connectors J1 and J2 for PCI, and J3 and J5 for I/O. J4 is not fitted to the board. See FIGURE 5-1 and FIGURE 5-2 for top and solder-side views of the board.

FIGURE 5-1 Netra CP2160 Board Layout

This is an illustration of a typical Netra CP2160 board layout with its key components.

Note - The heat sink and the power module are shown as dotted lines in this diagram to illustrate the components on the board that lie beneath these devices.

FIGURE 5-2 Typical Netra CP2160 Board - Solder Side

This is an illustration of a typical solder side of a Netra CP2160 board.

A Netra CP2160 board functions as a satellite board or as a system host board. The board has the following I/O access:

Through the two Ethernet ports and one serial port on the front panel.

Through the CompactPCI backplane: a transition card must be connected to provide rear connector access for two serial ports, two Ethernet ports and a USB port. Sun Microsystems offers a compatible XCP2160-TRN transition card
(375-0120-xx). This card is recommended for use, but OEM customers may design their own transition cards for use instead.

Through one or two PMC card interfaces provided to accept up to two IHV-supplied PMC I/O cards.

Through one or two IHV-supplied PIM modules that can duplicate front-panel PMC I/O ports. The PIMs attach to interfaces on a transition card and bring the ports out to its panel at the rear of the enclosure. See Section 5.4.4, PMC and PIM Interface for further details.

The front panel of the Netra CP2160 board has two PMC module slots, two Ethernet ports, a serial port and the following reset pushbuttons and status LEDs:

ABORT - pushbutton (XIR)

RESET - pushbutton (POR)

USER - orange/green

READY - green

Blue LED for hot-swap

FIGURE 5-3 Typical Netra CP2160 Board Assembly With Heat Sink

This illustration shows a typical Netra CP2160 board assembly with the heat sink.

5.2 Detailed Description

A simplified schematic diagram is shown in FIGURE 5-4.

FIGURE 5-4 Netra CP2160 Board Functional Block Diagram

This block diagram is a simplified schematic diagram of the Netra CP2160 board.

The L2-cache is integrated into the UltraSPARC IIi processor package. This processor is supported by SDRAM memory that is soldered onto the board and is also available in plug-in module form.

Apart from incoming interrupts, the processor handles all I/O through its built-in
66 MHz, 32-bit PCI bus interface. This interface is used to connect to a Sun Advanced PCI Bridge (APB) that services two 33 MHz 32-bit downstream interfaces, PCI bus A and PCI bus B.

PCI bus A connects to a nontransparent PCI bridge (21555 NTB), which services the principal PCI bus connection to the CompactPCI backplane through its connectors J1 and J2. In a system host role, a PCI bus arbiter provides CompactPCI bus arbitration signals for the CPCI backplane bus. It also supplies clocks for the CPCI bus. The arbiter is only active if the system host board is installed into the system slot and functions in a system host role. When the board functions as a satellite board, the CPCI bus arbiter is disabled by the system management controller (SMC). (See Section 5.4.3.1, Arbitration in System Controller Role for details).

PCI Bus B connects the APB to each of two PCIO-2 South Bridge packages, PCIO-2 A and PCIO-2 B. See Section 5.4.2, PCIO-2 Devices and EBus Paths for more details.

In addition, The PCI bus B from the APB connects to each of two 33 MHz, 32-bit PMC interfaces on the host board. See Section 5.4.4, PMC and PIM Interface for more detail.

The SMC connects to:

The bus arbiter and clock generator, enabling it to control CompactPCI bus arbitration, clock, and reset functions.

The on-board I²C bus, enabling it to communicate with sensors and controls.

The User IPMI bus, enabling user management of other entities in the system. Peripheral hot-swap control is also enabled through this path.

The power module.

The SMC controls the startup of the board, because it activates the power module and can control the system reset signals. In addition, it handles hot-swap signals from the CompactPCI backplane, for example: ENUM, HEALTHY, BD_SEL, and PCI_RST (the PCI reset signal). See Section 1.3, Hot-Swap Support for more information on hot-swap.

The block schematic diagram of FIGURE 5-5 shows a more detailed block diagram of the Netra CP2160 board.

FIGURE 5-5 Netra CP2160 Board Detailed Block Diagram

This is a detailed block diagram of the Netra CP2160 board.

5.3 CPU and Main Memory Subsystems

This section describes the UltraSPARC-IIi processor and additional memory on the Netra CP2160 boards. FIGURE 5-6 shows the UltraSPARC IIi interfaces.

5.3.1 UltraSPARC IIi Processor

FIGURE 5-6 UltraSPARC IIi Interface

This diagram shows the UltraSPARC IIi interface.

The Netra CP2160 board uses the UltraSPARC IIi 650 MHz processor. The processor is housed in a 370-pin ceramic pin grid array (PGA) package. It typically dissipates no more than 25 W at 650 Mhz.

The UltraSPARC IIi processor is directly connected to the board SDRAM through a 72-bit ECC path. Dual address buses reduce capacitive loading and increase the memory density beyond that of unbuffered devices.

The CPU connects to the APB by means of a 32-bit, 66 MHz PCI interface which the APB in turn translates to two downstream 33 MHz PCI buses.

The UltraSPARC processor begins execution from a fixed image in a PROM that lies on EBus A. The processor accesses this EBus in a boot path that automatically includes the APB, PCIO-2 A (a South Bridge), and EBus A.

Processor resets are received from the system management controller (SMC). See Section 5.7, Resets and FIGURE 5-20 for more detail.

The various interrupts on the board are prioritized and encoded by the I-chip2 to appear at the UltraSPARC IIi processor as 6-bit parallel data. See Section 5.7, Resets for more information.

The processor I/O is run at a fixed VDDIO of 3.3V but the core voltage, VDDCORE, is adjustable and configured according to CPU speed, typically in the range of 1.3 V to 1.9 V.

JTAG/Test signals are available for use in boundary scan diagnostics.

5.3.2 Memory Address Mapping

The UltraSPARC IIi L2 cache megacell reserves a 2 GB region for cacheable main memory. The memory databus width and the module databus width are of equal size (64-bit data plus 8 bit ECC) so memory modules can be installed in mixed sizes.

The UltraSPARC IIi Address Data Generation Logic (ADGL) logically maps modules according to their size, rather than their physical location. The largest sizes are mapped to the lowest address ranges. Where modules of identical size are present, the lower slot number is mapped to the lower address range.

FIGURE 5-7 shows a memory mapping example.

FIGURE 5-7 Memory Mapping Example

This is an example of memory mapping on the CPU processor.

5.3.3 SDRAM Memory

FIGURE 5-8 SDRAM Memory Interface

This diagram shows the SDRAM memory interface with the CPU processor, the SMC and the motherboard.

The UltraSPARC IIi 650 MHz processor connects directly to the memory with a 72-bit ECC data bus. The memory can be either on-board SDRAM only or composed of an additional mezzanine memory module.

Each mezzanine memory module has two 100-pin male connectors on its bottom surface--these plug into corresponding female connectors on the system board. No more than one additonal memory modules may be added to the 1 Gbyte on-board memory.

Each module is equipped with a temperature sensor and a serial EEPROM device containing 256 bytes of presence detect data. The double size module (if used) also contains a PLL, which generates eight clock signals. Both the temperature sensor and the serial EEPROM are accessed using the two pin I²C protocol.

The memory block, whether on-board or a module, provides non-volatile serial memory to enable the Serial Presence Detect function. This memory can be interrogated by the SMC through the I²C interface.

5.3.4 Memory Components

This section describes additional memory available on the Netra CP2160 boards.

5.3.4.1 System (Boot) Flash Memory

The system flash resides in 1 Mbyte of space. It contains Common Operations and Reset Environment (CORE) firmware, Comprehensive POST, and OpenBoot PROM boot code. The system flash may be upgraded by running a program out of OpenBoot PROM or executing a Solaris software script. If the system flash becomes corrupted, contact your nearest Field Application Engineer.

5.3.4.2 User Flash Memory

The board is equipped with 8 Mbyte of user flash memory. You may use the flash memory for various purposes such as storage for RTOS, user data storage, OpenBoot PROM information, or to house dropins. Dropins simplify customizing a system for the user.

A userflash switch SW2501 determines whether the userflash is detected during OpenBoot PROM boot and whether it is write enabled (see Section B.4, Switch Settings).

5.3.4.3 NVRAM

The Netra CP2160 board does not have a battery back-up for the NVRAM. The NVRAM on this board functions as SRAM.

These boards use an 8K-bit X 8 timekeeper SRAM (NVRAM) package. This component provides:

A time-of-day (TOD) real-time clock.

8 Kbyte storage for environment variables, user modifiable. The Ethernet address and Host ID are stored in the system flash. These values are copied to the SRAM when the system is powered-on.

On firmware boot up, the Ethernet address stored in the SRAM is compared against the backup copy stored in the serial I²C EEPROM on the Netra CP2160 board and the SRAM is updated if it differs from the backup copy.

5.3.4.4 Serial I²C EEPROM

This device stores the backup copy of the board MAC address and Host ID in a removable serial EEPROM that is accessible through the I²C bus. This data is downloaded to the SRAM at the OpenBoot PROM level.

5.3.4.5 FRU ID I²C EEPROM

The FRU ID I²C EEPROM chip stores manufacturing-related information of the Netra CP2160 board This information is useful only when the Netra board is being serviced.

See Appendix C for details on accessing the FRU ID information for the board.

5.4 Bus Subsystems

There are four PCI buses on the board: three internal buses and the external CompactPCI bus that is driven to and from the backplane. One of the internal PCI buses, PCI bus B, is bridged to two lower-speed buses EBus A and EBus B. PCI bus A communicates with the CompactPCI backplane through the nontransparent PCI-to-PCI bridge (21555 NTB). This arrangement is shown in FIGURE 5-9.

FIGURE 5-9 Netra CP2160 Board PCI Bus Interface, 33MHz CompactPCI Bridge

This diagram shows the Netra CP2160 board PCI bus interface.

5.4.1 APB PCI Bus Interfaces

The UltraSPARC IIi CPU has an integrated 32-bit/66 MHz PCI bus interface. The Advanced PCI Bridge--acting as a North Bridge--splits this bus into two
32-bit/33 MHz PCI buses. Of these, the PCI A bus connects to the PCI non-transparent bridge which forms the interface to the CompactPCI backplane. The PCI B bus connects to two PCIO-2 bridges. Each of these bridges carry an EBus and peripheral interfaces at their other end.

5.4.2 PCIO-2 Devices and EBus Paths

The two PCIO-2 bridges connect between the APB PCI Bus B and their EBus and peripheral interfaces at their other end. Each of these bridges carry one EBus interface. The EBus interfaces are used to interface slower internal peripherals.

EBus A coming from PCIO-2 A :

System Flash EEPROM. The UltraSPARC IIi processor accesses system flash EPROM through the APB and PCIO-2 A to boot from location 0xF0000.0000.

User flash EPROM

NVRAM

Main PLD, which provides EBus decodes for chip select and CompactPCI arbiter control logic.

Serial I/O through a dual universal asynchronous receiver/transmitter (DUART) device which uses an RS232 transceiver device to support two independent RS232 style serial ports. The RS232 level signals feed to the XCP2160-TRN transition module through the CPCI J5 connector.

EBus B coming from PCIO-2 B :

System management controller (SMC). This path is the primary means of communication between the UltraSPARC IIi host and the SMC.

In addition, PCIO-2 A supports the MII Ethernet A port and USB A port. PCIO-2 B supports the MII Ethernet B port and USB B port.

5.4.3 CompactPCI Bus

The nontransparent bridge (NTB), in this case the Intel 21555 device, connects the 32-bit/33 MHz internal PCI bus A to the 64-bit/33 MHz CompactPCI backplane bus through CompactPCI connectors J1 and J2. This interface conforms to the PICMG 2.0 R3.0 CompactPCI Specification. FIGURE 5-10 shows the CompactPCI bus interface.

FIGURE 5-10 CompactPCI Bus Interface

This diagram shows the CompactPCI bus interface.

The arbiter--only used when the board functions in a system host board role--provides for orderly sharing of the CompactPCI bus among potential bus masters, or initiators. When the board performs in a system host board role, PCI clocks sourced from a clock generator on the board are driven to a CompactPCI CLK bus signal to all slots on the CompactPCI backplane.

5.4.3.1 Arbitration in System Controller Role

The Netra CP2160 board can be used as a system controller board or as a satellite board. When the Netra board is a system controller board, the arbiter is enabled by the SMC. When the Netra board is a satellite board, the arbiter is disabled by the SMC through a control signal (signal SYS-EN on J2/C2).

FIGURE 5-11 and FIGURE 5-12 illustrate the signal flows for the two board operations.

FIGURE 5-11 Netra CP2160 Board System Controller Board: REQ#/GNT# Signal Flow

This is an illustration of the Netra CP2160 system controller board: REQ#/GNT# signal flow.

FIGURE 5-12 Netra CP2160 Board Satellite Board: REQ#/GNT# Signal Flow

This is an illustration of the Netra CP2160 satellite board: REQ#/GNT# signal flow.

When the Netra CP2160 board is operating as a satellite board, the arbiter is disabled (through a control signal from the SMC module). When disabled, the arbiter tristates REQ1# through REQ6# and GNT1# through GNT6# and pulls them to a known state. The multiplexing, switching, or logic used to control the flow of the arbiter signals comply with all requirements of the CPCI specification, notably the requirements for single loads and stub length.

5.4.4 PMC and PIM Interface

The PCI mezzanine card (PMC) interface is defined by IEEE and PICMG standards:

IEEE P1386, presently in draft form, defines the Common Mezzanine Card (CMC) mechanical profile (common because this definition, for example, can also apply to a VME rendering)

P1386.1 defines the PCI electrical interface through its connectors Pn1/Jn1 through Pn4/Jn4

PICMG 2.3 R1.0, PMC on CompactPCI Specification maps the PMC signals from the Jn1 through Jn4 connectors on the CompactPCI board through the CompactPCI backplane connections. In the case of the 6U products discussed here, these connections are routed to CompactPCI J3 and J5 connectors.

The PMC interface enables you to use Independent Hardware Vendor (IHV) PMC to implement additional I/O from the host at the system integration level.

The number of PMCs that can be used with the Netra CP2160 board varies according to the size of modular memory installed on the board. Refer to TABLE 5-1 for details.

TABLE 5-1 PMC Slots Available
Memory Modules Installed	Number of PMC Slots Available
No modular memory installed	Two
Single-wide module installed	One
Double-wide module installed	Zero

A Sun XCP2060-TRN I/O transition card fitted to the rear of the backplane provides slots for PIM cards. A PIM card enables rear I/O functions when paired with a PMC card installed on the front panel of the board.

A PIM must have a corresponding PMC in the front slot because the PMC board performs an adapter function between the PCI bus B and the user I/O signals passed through J5 to the PIM slot on the transition card. When a PMC that has a front-panel connector is used with a PIM, jumpers are typically set to disable its front I/O operation.

FIGURE 5-13 illustrates the interconnection between PMC and PIM slots for installed PIMs.

FIGURE 5-13 PIM Installation Configuration

This figure shows the PIM installation configuration.

FIGURE 5-14 shows the PMC A and card attachment to a Netra CP2160 board. There is a second PMC connector, PMC B, adjacent to the first (see FIGURE 5-15).

FIGURE 5-14 Data Paths in PCI Mezzanine Module Interface on Host Board

This is a figure of the data paths in PCI mezzanine module interface on a host board.

The APB on the Netra CP2160 board supplies PCI bus signals to PMC connectors J21 and J22. The PMC card logic decodes its specific I/O interface, which it makes available at the front panel.

64-pin PMC connectors J23 and J13 are not fitted to these Netra boards. These connectors are specified for expansion for 64-bit PCI (it carries the upper 32 bits), which is not provided. A 64-bit capable PMC card can function in these slots but its bus interface is constrained to 32 bits.

J24 is specified for user I/O and carries PMC signals to CompactPCI backplane connector J3. If a transition card is installed, this J5 I/O is conditioned by an IHV-supplied PIM to provide matching I/O on the enclosure back panel. Its backplane I/O is routed to CompactPCI/J5 connector.

In the case of the PMC B card for the Netra CP2160 board, J11 and J12 are similarly connected to the APB but the user I/O from J14 is routed out of CompactPCI connector J3.

FIGURE 5-15 PMC Connector Interfaces on Netra CP2160 Board.

This diagram shows the PMC connector interfaces on the Netra CP2160 board.

5.4.5 I²C and IPMI Channels

The I²C paths are shown in FIGURE 5-16. I²C communication is used:

To implement the IPMI interface for system management.

To provide a means of performing Local Advanced System Monitoring (ASM) which monitors--and controls where appropriate--local board or chassis "housekeeping" functions. These functions include: monitoring of temperature, FRU ID, MAC address, and memory type and size.

To provide an interface for user monitoring and control, for example chassis temperature or fan operation.

Each I²C device on the board uses common address pins. The devices are distinguished by the internal device ID. All I²C devices are supplied from early power before backend power is established (see Section 5.8, Power Subsystem for further details).

FIGURE 5-16 Netra CP2160 Board and CP2160 I ²C Paths

This diagram the I2C paths on the Netra CP2160 board.

5.5 System Input/Output

FIGURE 5-17 I/O Interfaces

This diagram shows the I/O interfaces between the CP2160 board and its front panel as well and on the transition card through the backplane.

FIGURE 5-17 shows the I/O for the Netra board. The I/O functions can be categorized into four groups which are described in the following sections.

5.5.1 Front-Panel I/O

FIGURE 5-18 illustrates the indicators and I/O connectors on the Netra CP2160 board front panel. The Netra CP2160 board front panel connectors, buttons and LEDs are described below:

Two peripheral mezzanine card (PMC) I/O bezels

Two RJ45 Ethernet connectors (with built-in transformer) connected to two separate PHYs, which are muxed with the other two PHYs of CPCI connector J5

A serial connector (mini-D9) which is also connected to serial port A of the 16552 UART on the board

ABORT - An abort pushbutton; passes an XIR signal to the SMC

RESET - A reset pushbutton; passes an Power-on-Reset (POR) signal to the SMC

USER - An orange and green (two color) LED that is defined by the user. The default function for the green LED signals that the board is at OK status. The colors are controlled by SPARC via SMC. See the Netra CP2000 and CP2100 Series CompactPCI Boards Programming Guide for Solaris Operating Environment, (816-2485-xx) for information on programming the user LED. You can access this document at:

http://www.sun.com/products-n-solutions/hardware/docs/CPU_Boards/

READY - A green power LED, sourced from the power module.

A blue LED for hot-swap status, sourced from the SMC.

FIGURE 5-18 Netra CP2160 Board Front Panel

The illustration shows the Netra CP2160 board front panel.

5.5.2 PMC Interface

The host board includes two PMC front-panel I/O cutouts to enable attachment of up to two PMC expansion cards. When installed, these cards access a PCI bus through compatible connectors provided on the host board. See Section 5.4.4, PMC and PIM Interface.

5.5.3 Backplane I/O

Most of the I/O channels to or from the board are passed to CompactPCI connectors J3 and J5; these channels are accessible from external connections on a transition card connected at the rear of the CompactPCI backplane. Connector J4 is not populated on these host boards to prevent contention with H110-compliant backplane signals. Contact assignments for these connectors are shown in Section B.3, CompactPCI Backplane Connectors. For location of the connectors, see FIGURE 5-1.

5.5.3.1 J3 Signals

The user-defined PMC I/O signals from the two PMC Jn3 connectors pass to their external interface through the J3 CompactPCI backplane connector (see Section B.3, CompactPCI Backplane Connectors).

5.5.3.2 J5 Signals

The following signal sets pass through the J5 CompactPCI backplane connector to connect to an external interface connector on the transition card:

Two TP Ethernet channels from the PHYs

Two serial channels

Two USB channels

An I²C channel

PMC I/O

5.6 System Management Controller

The System Management Controller (SMC) subsystem is one of the most important components of the system board. This subsystem provides a variety of service functions related to assuring availability of the system. These functions contrast with the board functions that execute applications.

The SMC consists of a small microcontroller with an SRAM for a software stack and nonvolatile memory for program storage and data logging. The SMC is modular in character, but is physically embedded into the circuitry of the Netra CP2160 board. FIGURE 5-19 shows its functional relationship with the system.

FIGURE 5-19 System Management Controller Interface

This diagram shows the system management controller interface with the Netra CP2160 board.

The SMC hardware and firmware implements the functions of system management and hot-swap control.

Note - Although the hardware and firmware functions are architecturally separate, reference to the SMC subsystem in this document--whose description is hardware oriented--refers to both functions.

The SMC controls the on-board CompactPCI interface components for the hot-swap process. It coordinates the state of the 21555 PCI bridge, the arbiter functions, and the switched connection of critical CompactPCI signals to the bus.

In performing these functions, the design maintains conformance with the PICMG CompactPCI core specification and the PICMG CompactPCI hot-swap specification: See Appendix D for references to these documents. The main features that are supported by the SMC subsystem are:

Coordinates and controls local resets on the system board during power-on reset, watchdog timeout, software initiated reset, and as a result of user intervention such as pushbutton reset or backplane reset.

Enables operation as either a system host board or as a satellite board in standard CompactPCI backplanes.

Supports a command and communications interface between the UltraSPARC IIi host processor and the SMC microcontroller by means of an interconnecting
EBus. This interface accommodates a command suite from the UltraSPARC processor to the SMC and supports bidirectional interrupt between the UltraSPARC processor and the SMC.

Supports signals that are critical to system configuration or hot-swap reconfiguration. These signals accomplish CompactPCI reset control, bus enumeration, and configuration of CompactPCI bus arbitration. These signals apply differently depending upon whether the board acts as a system host board or a satellite board.

A satellite board responds to the CompactPCI RST, ENUM, HEALTHY, and BD_SEL signals from the active system host board (provided that this host provides HA hot-swap functions through the CompactPCI bus. See also Section 4.6.2, PCI_RESET# Polling on the Satellite Board). The satellite board also sets a REQ signal to the arbiter on the system host board and awaits a corresponding GNT from it.

Note - This board does not provide HA hot-swap control for peripherals.

A system board provides the CompactPCI peripheral reset signal PCI_RST and reads the CompactPCI bus enumeration signal ENUM. Its CompactPCI arbiter is configured to issue GNT signals to peripherals in response to their REQ requests.

Implements a two-level watchdog timer for the SMC processor and for the host processor.

Supports two I²C ports. One of the I²C ports carries an IPMI bus that is routed through CompactPCI backplane connector J1 to enable communication with other SMCs in the system. The other I²C port serves a multiplexer that splits its input into two channels: one channel provides communication with on-board devices, (for example for temperature or FRU information); the other channel is for user functions and is passed out of J5 connector.

Uses an EEPROM for storing non-volatile data such as the host board ID MAC address.

Supports two system controller models of CompactPCI Hot Swap system architecture. See Section 1.3, Hot-Swap Support; also see Appendix D for a reference to the PICMG CompactPCI hot-swap specification.

Communicates with other SMCs in the CPCI system using the IPMI protocol over a backplane link, in accordance with the PICMG CompactPCI hot-swap specification. The SMC:

Assumes a Baseboard Management Controller (BMC) role when the host board is installed in a system host slot.

Responds to commands from the active BMC when the host board is installed in a peripheral slot.

Enables Local Advanced System Monitoring (ASM); ASM is a management scheme that monitors--and controls where appropriate--local board or chassis "housekeeping" functions through the on-board I²C interface. Such functions include (see also Section 4.6, ASM Support at OpenBoot PROM):

Temperature sensing

Power supply voltage sensing

Power supply module on/off control

Memory module and board ID detection

Supports flash update - The SMC firmware supports external update of its flash RAM (see Chapter 4).

Acts as a peripheral management interface, which includes:

IPMI communications with Baseboard Management Controller

Handling of hot-swap (HEALTHY/ENUM/PRESENT) related signals

Receiving system and CompactPCI reset events to generate local board reset

For full details on SMC and reset information, refer to Chapter 4 and the Netra CP2160 board web site:

http://www.sun.com/products-n-solutions/nep/hardware/boards/cp2160/

5.6.1 Watchdog Timer

In the Netra CP2160 board, the SMC implements a two-level watchdog timer. The host-SMC command interface defines communication between host and SMC. The host and the SMC constantly communicate with each other when the watchdog timer is enabled. The SMC monitors the heartbeat of the CPU processor host. The heartbeat is sent in the form of a reset watchdog timer that is sent from the CPU to the SMC. The watchdog timer must be programmed to ensure that it does not get too close to the expiration. There should be some time accounted for the latency overhead or any unexpected event that may delay transmission of the heartbeat. For full details on programming the watchdog timer, refer to the Netra CP2000 and CP2100 Series CompactPCI Boards Programming Guide (816-2485-xx).

The two levels of the watchdog timer are as follows:

Countdown register timer (16 bits, 100 msec. resolution)

Pre-timeout timer (1 sec. resolution)

The two watchdog timers are enabled by messages sent over the host-SMC command interface using the set watchdog timer command. The commands enabled in the host-SMC command interface for watchdog timer functionality are:

smc-reset-wdt

smc-set-wdt

smc-get-wdt

The uses of these functions are shown in TABLE 5-2.

TABLE 5-2 Host-SMC Commands for Watchdog Timer
Host-SMC Command	Uses
`smc-reset-wdt`	Starts and restarts watchdog timer from the initial countdown value
`smc-set-wdt`	Initializes, configures and stops the watchdog timer
`smc-set-wdt`	Retrieves current settings and present timer value of watchdog timer

5.7 Resets

This section provides details on resets for the Netra CP2160 board.

FIGURE 5-20 Simplified Reset Paths

This diagram shows a simplified set of reset paths.

Parts of the system are powered by early power before the SPARC domain receives power (backend power). See Section 5.8, Power Subsystem. At the onset of early power, the SMC is reset by its component microcontroller. When backend power rails are at their specified voltages and if the SMC has the power module turned on, the SMC receives the PWR_OK signal and in turn resets the backend members of the system. Note that:

When the SMC is reset, the whole system is reset.

When the CPU is reset, the CPU I/O and the 21555 NTB is reset.

The SMC can reset the 21555 NTB without resetting the CPU.

For detailed information on configurable reset implementation by SMC firmware, see Section 4.7.1, SMC Firmware Reset Modes for System Slot and Peripheral Slot Operations.

FIGURE 5-21 Simplified CPU Subsystem Reset Architecture

This diagram shows the simplified CPU subsystem reset architecture.

5.8 Power Subsystem

FIGURE 5-22 shows a simplified schematic diagram of the power subsystem. This subsystem can power the board to support a hot-swap environment.

FIGURE 5-22 Power Distribution Block Diagram

This is a block diagram showing the power distribution for the Netra CP2160 board.

Note - In FIGURE 5-22 I²C power is derived from early power.

The Netra CP2160 board sequences power in two time-separated domains:

Early Power domain

SPARC Power domain--this is the Backend Power in the PICMG hot-swap specification.

Early power is applied to the board from backplane long pins (LP in the figure) as the board is inserted. Early power current flows to board subsystems:

Power Module - supplies precharge current to the CompactPCI bus interface component.s

SMC - needed to control logical state of the CompactPCI interface circuits as they are connected.

IPMI/I²C subsystems - needed for management/monitoring functions at this stage; I²C power also extends to the transition card.

The 21555 NTB and CompactPCI Interface component - must be placed in a known state during attachment to the CompactPCI bus.

5.8.1 Power Module

FIGURE 5-23 shows a schematic diagram of the power module. This subassembly is integrated with the Netra CP2160 board.

FIGURE 5-23 Power Module Interface

This diagram shows the power module interface.

This subsystem performs the following functions:

Generates Vp, the CompactPCI hot-swap precharge bias voltage using early power

Generates V_DDCORE , the UltraSPARC processor core voltage supply.

Controls and gates 5V, 12V, 3.3V and -12V

Automatically shuts down in case of overcurrent or overvoltage

Asserts the PWR_MOD_OK signal

The power module is controlled by the SMC and the power on/off signal. Functions controlled include core voltage, output level, and module on or off state. There are also automatic controls within the power module, for example, overcurrent shutdown, and voltage regulation.

The power module has a DIP switch with six preset default settings. These switches are for factory use only (see FIGURE 5-24 for location). The user must not change DIP switch settings.

FIGURE 5-24 DIP Switch Settings on Power Module

This is an illustraton showing an enlargement of the DIP switch settings on the power module.

Note - The preceding figure is only an example of the types of settings you might find on the board youn receive. The DIP switch settings on your board might have been set differently in the factory.

5.8.2 Early Power and IPMI Power

If the system power for the backplane fails, the SMC can use IPMI power, typically supplied from an uninterruptible power supply (UPS), instead of early power from the CompactPCI backplane. The backplane is provided with IPMI power pins for this purpose. FIGURE 5-25 shows the circuit arrangement that selects between these power sources.

FIGURE 5-25 Selection Between Early Power and IPMI Power

This drawing shows the selection between early power and IPMI power.

5.8.3 Transition Card Power Distribution

FIGURE 5-26 shows the power rail routing to the transition card. The XCP2160-TRN
I/O transition card is powered from the Netra CP2160 board rather than directly from the backplane. The transition card must always be connected to the backplane before the chassis is powered. Always install the transition card before the Netra CP2160 board in the chassis. For details on using a transition card, see Chapter 3.

FIGURE 5-26 Transition Card Power Supply Routing

This is a drawing of the transition card power supply routing.

Note - Some V(I/O) power lines are routed into J2 of the motherboard; this is not shown in the figure for clarity.

5.9 CompactPCI Interface

This section provides information on CompactPCI and the Netra CP2160 board interface requirements specifications and CompactPCI signal interface.

5.9.1 CompactPCI Interface Requirements

TABLE 5-3 lists the requirements for Netra CP2160 boards as defined by the PICMG 3.0 CompactPCI and Netra CP2160 board design requirements specifications:

TABLE 5-3 Compact PCI Interface Requirements
Requirement	Description
Bus termination	10 ohm CPCI series termination resistor shall be located 0.600 max. from J1/J2 pin on all required signals.
Stub length	CPCI pull-up stub length 0.500 inches max.
5V VIO	Provides 1.0K ohm +/-1% pull-up for all required CompactPCI bus signals for use in 5V CompactPCI signaling environment.
System and peripheral slot operation	Provide control to disable both pull-ups (In a CompactPCI system, only the board in the system slot can provide the bus pull-ups).
Hot swap	Provide 1V +/-20% precharge bias voltage (Vp) for all required CompactPCI bus signals.
Max capacitive load per pin and system and satellite slot operation	Provide an auxiliary output for selected CompactPCI bus signals (those that are shared between the bridge and external arbiter)

5.9.2 CompactPCI Signal Interface

The tables in this section list the CPCI signal interface description and the CPCI connector power signal interface. The primary side of the bridge is attached to the 64-bit CompactPCI bus.

TABLE 5-4 Compact PCI Signal Interface
Signal	Description	Type	Notes
P_AD<63..0>	Addr/Data Bus	I/O
P_CBE<7..0>	Command/ Byte Enable#	I/O
P_CLK	Clock Input	I	33 MHz Compact PCI Bus Clock.
P_IDSEL	ID Select	I
P_INTA_L	Primary Bus Interrupt	OD	Needs external pullup. Assert when: Primary doorbell register bit set. I20 outbound queue not empty. Subsystem event bit set.
P_GNT_L	Bus Grant	I/O	Shared with arbiter.
P_REQ_L	Bus Request	I/O	Shared with arbiter.
P_PAR	Parity for lower 32 bits	I/O
P_PAR64	Parity for upper 32 bits	I/O	Requires external pullup.
P_PERR_L	Parity Error	I/O	Requires external pullup.
P_SERR_L	System Error	I/O	Requires external pullup.
P_RST_L	Bus Reset	I
P_VIO	Signaling Environment 3.3V or 5V	I
P_DEVSEL_L	Device Select	I	Requires external pullup.
P_FRAME_L	Frame	I	Requires external pullup. Shared with arbiter.
P_STOP_L	Stop	I	Requires external pullup.
P_IRDY_L	Initiator Ready	I/O	Requires external pullup. Shared with arbiter.
P_TRDY_L	Target Ready	I/O	Requires external pullup. Shared with arbiter.
P_REQ64_L	64 -bit transfer request	I/O	Requires external pullup.
P_ACK64_L	64 -bit transfer ack	I/O	Requires external pullup.

TABLE 5-5 CPCI Connector Power Signal Interface
Voltage	CPCI Pin(s)	Net Name	Notes
3.3V	J1-C6 & C22	BP_EP_3.3V	Long pin
3.3V	J1-A15, A17, A19, A21, A23, C10, C18, & D25	EP_3.3V	Medium pin
5V	J1-D3 & D23	BP_EP_5V	Long pin
5V	J1-A1, A25, B2, B24, E1, & E25	EP_5V	Medium pin
+12V	J1-D1	BP_12V_POS	Medium pin
-12V	J1-B1	BP_12V_NEG	Medium pin
3.3V or 5V	J1-C4	BP_EP_VIO	Long pin
3.3V or 5V	J1-C8, J1-C16, J1-C24, J2-A4, J2-C5, J2-C7, J2-C9, J2-C11, J2-C13	EP_VIO	Medium pin

Note - The early power voltages supply critical circuits such as SMC, CPCI interface circuits, and power module control circuit.

5.10 Interrupts

The Netra CP2160 board interrupts are listed in TABLE 5-6. These are processed and encoded by the I-Chip2 ASIC. This device assigns equal priority to all interrupting devices. When two devices need servicing at the same time, the I-Chip prioritizes using its internal round-robin scheduling scheme. The resultant vector is passed to the processor as a 6-bit parallel word. The ultimate interrupt priority is resolved in the UltraSPARC IIi processor.

TABLE 5-6 Interrupt Assignments
Offset	Interrupt	INT#	Priority
0	CPCI_INTA ^[1]	7	7
1	CPCI_INTB	5	5
2	CPCI_INTC	15	5
3	CPCI_INTD	2	2
4	SPARC_H_INT ^[2]	F	7
5		D	5
6		LD	5
7		A	2
8	PCIO-2_A_ENET	17	6
9		38	5
A	PMC1_INT_A	10	2
B	PMC1_INT_B	12	1
C	PMC1_INT_C	18	6
D	Not on IChip2	39	4
E		0	2
F	DOORBELL	1A	1
10	DUART_SER_A	6	6
11	MCA_INT_L	4	4
12		3	3
13		1	1
14	DUART_SER_B	E	6
15	PMC1_INT_D	C	4
16	PMC2_INT_A	B	3
17		9	1
18		16	6
19	PCIO-2_B_EBUS	14	4
1A		13	3
1B		11	1
1C	PCIO-2_B_ENET	1E	6
1D	PCIO-2_A_EBUS	1C	4
1E	SPARC_L_INTSPARC_L_INT and SPARC_H_INT are driven by the SMC module.	1B	3
1F		19	1
20	PMC2_INT_B	20	3
21		21	3
22	PMC2_INT_C	22	2
23		24	8
24	PCIO-2_A_USB	1F	7
25		25	8
26	PCIO-2_B_USB	28	7
27	PMC2_INT_D	29	8
28	I2C_GLOBAL_INT	2A	2
29		2B	4
2A		2C	4
2B	SYNC_SER_L1	2D	7
2C			RES
2D			RES
2E			RES
2F			RES
graphic 1 23 from INR	CPCI_SERR_L ^[3]	23	5
graphic 2 26 from INR		26	5

5.11 Chip-Select PLD Registers

The TABLE 5-7 lists the chip-select PLD registers.

TABLE 5-7 Chip-Select PLD Registers
EBus Address	R/W	Name	Description
0x20.000	W	DUART_RESET	Any write operation to this register toggles the DUART reset line.
0x20.0001	R/W	PMC_BUSMODE	Bit 4: PMC_BUSMODE4_L. R/W; boot default = 0 Bit 3: PMC_BUSMODE3_L. R/W; boot default = 0 Bit 2: PMC_BUSMODE2_L. R/W; boot default = 1 Bit 1: PMC_BUSMODE1_L. Read only; writes are ignored. Bit 0: PMC_BUSMODE0_L. Read only; writes are ignored.
0x20.0002	R/W	WRITE_PROTECT	Bit 1 : I2C write protect 1 = protected 0 = unprotected Boot default is 0 Bit 0: User flash write protect 1 = protected 0 = unprotected Boot default is 0
0x20.0003	R	PLD_REV	Read returns the PLD firmware revision, for example, 0xB3.
0x20.0004	R/W	SPARC_INT	SMC_SPARC_L_INT_L mask bit. SMC_SPARC_L_INT_L enters the PLD. PLD_SMC_SPARC_L_INT_L is the masked output. 0 = masked HIGH 1 = not masked Boot default is 1.
0x20.0005	R/W	INTx	CPCI interrupts mask register. CPCI interrupts enter PLD as SW_CP_INTx_L. Masked outputs are PLD_CP_INTx_L. Mask behavior: 0 = masked HIGH 1 & CP2160 is SBC = unmasked 1 & CP2160 is not SBC = TRISTATE Boot default = 1 Bit assignments: Bit 3 = INTA_L Bit 2 = INTB_L Bit 1 = INTC_L Bit 0 = INTD_L
0x20.0006	R/W	DOORBELL	BRG_S_INTA_L mask bit BRG_S_INTA_L is the input to the PLD PLD_BRG_S_INTA_L is the masked output 0 = masked HIGH 1 = unmasked Boot default = 1
0x20.0007	R/W	TEST	For development use. May be written with any value and read.
0x20.0009	R/W	USERFLASH_SELECT	Bit 7: PLD_FLASH1_SEL (Read only) Bit 6: PLD_FLASH0_SEL (Read only)

Note - The registers in the chip-select PLD are mirrored in the EBus address space.

5.12 SMC PLD Registers

TABLE 5-8 shows the SMC PLD registers.

TABLE 5-8 SMC PLD Registers
EBus Address	R/W	Name	Description
0x1FF.F320.FF00		SMC_INT0 Register No. 1	Bit 7: PWR_MOD_OK signal Bit 6: Latched cPCI RST# 0 = cPCI RST# was asserted 1 = cPCI RST# has not been asserted Bit 5: PB_RST_L signal Bit 4: PB_ABORT_L signal Bit 3: SPARC_RST_21554_L signal Bit 2: BKRST_IN_L signal Bit 1: BP_DEG_L signal Bit 0: BP_FAL_L signal Any of the bits asserting LOW initiates an assertion of SMC_INT0_L.
0x1FF.F320.FF01	R	SMC_INT_0 Register No. 2	Bit 7: SERR_L signal INVERTED Bit 6: Non-latched PCI RST# signal Bit 5: IPMI power status 0 = no ipmi_pwr in 1 = ipmi_pwr in Bit 4: Option switch #2 status Bit 3: Option switch #1 status Bit 2: Reserved Bit 1: Reserved Bit 0: Reserved
0x1FF.F329.FF02	R/W	General purpose I/O	Bit 7: bp_GPIO_j4e1 GPIO Bit 6: bp_pwroff_j4c10 power Bit 5: sys_rst_set Bit 4: bkrstout_set Bit 3: 21554_rst_set Bit 2: xir_out_set Bit 1: pb_rst_set Bit 0: rst_j1c5_set All bits default HIGH.
0x1FF.F320.FF03	R/W R/W	FIFO/Address register	Bits 7-5: Address FIFO Bits 4-0: ADDR3 Register Bit 4: block PRST, default LOW Bit 3: block cPCI RST#, default HIGH Bit 2: enable NVRAM, default LOW Bit 1: PWR_MOD_ON, default HIGH Bit : SYSEN_ON_L, default LOW
0x1FF.F320.FFFF	R	Revision	SMC PLD Revision Level

^{1 (TableFootnote) CPCI_INT_A is shared with the Bridge Secondary side interrupt.}

^{2 (TableFootnote) SPARC_L_INT and SPARC_H_INT are driven by the SMC module.}

^{3 (TableFootnote) CPCI_SERR_L is masked at the PLD.}