Such duplication is error-prone; if a new object file is added to the system, we might add it to one list and forget the other. We can eliminate the risk and simplify the makefile by using a variable. Variables allow a text string to be defined once and substituted in multiple places later (see How to use variables).
It is standard practice for
every makefile to have a variable named objects,
OBJECTS,
objs,
OBJS,
obj,or
OBJ
which is a list of all object file names. We would define such a variable,
objects,
with input like the following in the makefile.
Then, each place we want
to put a list of the object file names, we can substitute the variable’s
value by writing ‘$(objects)’
( for more information, see How
to use variables). The following example shows how the complete
simple makefile looks when you use a variable for the object files.
edit : $(objects)
cc -o edit $(objects)
main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
command.o : command.c defs.h
command.h
cc -c command.c
display.o : display.c defs.h
buffer.h
cc -c display.c
insert.o : insert.c defs.h buffer.h
cc -c insert.c
search.o : search.c defs.h buffer.h
cc -c search.c
files.o : files.c defs.h buffer.h
command.h
cc -c files.c
utils.o : utils.c defs.h
cc -c utils.c
clean :
rm edit $(objects)