Sun Fire 15K/12K Systems
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| Sun Fire 15K/12K Systems
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Glossary |
The address repeater is used on slot 0 and slot 1 boards. Implements the on-board system address bus. Connects four CPUs (or two I/O controllers) to the address controller on the expander board.
automatic system recovery (ASR)
An automatic system recovery provides system operation in the event of a hardware failure. Identifies and isolates a failing hardware component, and builds a bootable system configuration without the failed hardware component.
The combination of an expander board, a slot 0 board, and a slot 1 board.
boot bus controller (SBBC) ASIC
The boot bus controller is used on slot 0 and slot 1 boards. Provides a console-bus-slave interface to PROM bus, JTAG, and I2C devices for board initialization. When used with CPUs, provides a boot-bus path to POST code.
Coherency directory cache inside the system address controller (AXQ) ASIC. Caches recent memory tag states stored in the ECC bits of memory to speed up accesses to cache lines on other boardsets.
Concurrent service is the ability to service various parts of a machine without interfering with a running system.
The Control board connects into one of two control slots on the Sun Fireplane interconnect. Consists of a centerplane support board, a System Control board, and a peripheral board.
A slot 0 board that holds four CPUs, each of which controls eight DIMMs.
The data arbiter is used on the Sun Fireplane interconnect to control the 18x18 data crossbar.
The data multiplexer is an 18x18 data crossbar that connects the system data interfaces on each expander board to the Sun Fireplane interconnect.
data path controller (SDC) ASIC
The data path controller is used on the slot 0 and slot 1 boards to controls the on-board system data path. Repeats the console bus to the two on-board boot-bus controllers.
The data switch is used on the slot 0 and slot 1 boards to connect the on-board system data path to the off-board system data path.
Dual CPU data switch ASIC that connects two CPUs and two memory units to the data switch ASIC.
A domain set is the combination of an SRD and its client domains.
The domainstop is the error isolation between itself and the client domains.
The process of activating or deactivating devices such as boards and power supplies, in a running Solaris operating environment while user applications continue.
The expander board connects into the Sun Fireplane interconnect at the slot 0 and slot 1 sockets.
Gigabyte per second of capacity = 230 = 1,073,741,824 bytes
Active device that can be installed and removed from a running system for dynamic reconfiguration.
Assembly that holds two 33-MHz standard PCI cards and two 66-MHz standard PCI cards. The PCI cards can be hot-swapped from the I/O slot while the system is in operation for dynamic reconfiguration.
Joint Test Action Group. An IEEE standard (1149.1) for serial scanning of chip internal registers.
Latency is the time for a single data item to be delivered from memory to a CPU.
The link controller is used on the link board to connect the system interconnect to three dual-simplex inter-cabinet optical fiber cables.
A linked domain is when a domain is removed from an inter-domain network.
A I/O slot 1 board that holds two CPUs (without memory).
Megabyte of capacity = 220 = 1,048,576 bytes.
A slot 1 assembly that holds two PCI controllers, each of which controls one 33-MHz standard PCI card and one 66-MHz standard PCI card. PCI cards are mounted in a hot-swap cassette.
The PCI controller is used on the PCI board and the link board to connect the system interconnect to one 33-MHz PCI bus and one 66-MHz PCI bus.
A passive hot-swap carrier that adapts standard PCI pins to connectors.
The hardware components powered by a group of 48-VAC power supplies.
A recordstop if a nonfatal error such as correctable single-bit errors in a data path.
response multiplexer (RMX) ASIC
The response multiplexer is an 18x18 crossbar that transmits transaction responses and connects together the address controllers on each expander board.
A mode of the system interconnect that enables multiple snoopy coherence domains to be connected together.
A board that has an off-board bandwidth of 4.8 Gbytes per second. One type of slot 0 board, the CPU/Memory board, is used in the Sun Fire 15K/12K systems.
A board that has an off-board bandwidth of 2.4 Gbytes per second. Three slot 1 board types are used in the in Sun Fire 15K/12K systems: the PCI board, the link board, and the MaxCPU board. All three of these slot 1 board types are unique to the Sun Fire 15K/12K systems.
A split expander is two system boards in a board set that are in separate domains.
Address bus containing a maximum snoop rate of 150 million snoops per second or a 9.6-Gbytes per second data rate.
The interconnect architecture used by the UltraSPARC III Cu generation of CPUs. This architecture is the physical active-logic centerplane that implements the system address and data crossbars.
Sun Fireplane interconnect architecture
The cache-coherency protocol and set of address transactions that are used by all UltraSPARC III Cu CPU based systems.
Sun Fireplane interconnect data path
The point-to-point data protocol used between the DCDS and DX ASICs.
system address controller
(AXQ) ASIC
The system address controller connects the address repeaters on the slot 0 and the slot 1 boards to the Sun Fireplane interconnect address and response crossbars. Used on expander boards.
The system board set connects into one of 18 system slots in the Sun Fireplane interconnect with the expander board. Contains slot 0 boards and slot 1 boards.
The System Control board set connects into one of two system control slots in the Sun Fireplane interconnect with the centerplane support board. This board set contains the System Control board and a system control peripheral board (DVD-ROM, tape drive, hard drive).
system data interface (SDI) ASIC
The system data interface is used on the expander boards. This interface connects the data switches on the slot 0 and the slot 1 boards to the Sun Fireplane interconnect data crossbars.
The UltraSPARC III Cu CPU is used on the CPU/Memory board and the MaxCPU board (first CPU model of the Sun Fireplane interconnect generation).
Removing a domain from the inter-domain network.
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